Part 2
Bitcell Comparison
Figure-1) ECL (Harper) bitcell with parallel schottky diodes
Figure-2) CTS bitcell with schottky access diodes
A key issue at this point is how to model the two bitcells and be accurate enough mathematically to provide reasonable simulation behavior when compared to silicon implementation. For this analysis, we need SPICE models for the bipolar transistors (NPN and PNP) and a schottky barrier diode model.
This next section defines the analysis methodology and we get started with a SPICE simulation CAD tool freely available on the Internet called "LTspice".
The analysis is only as good as the device models and the skill of the circuit designers. There may be several different kinds of analysis modes that a designer is interested in (we will discuss this later in greater detail, but, this is usually driven by the team's methodology and the "vision" of the management team). For example, the project may be in the early stages of "feasibility" assessment and a highly accurate device model might not be ready. We resort to "paper models" (which means that they are rough mathematical transistor models that get you into the ballpark of the new technology, but you cannot reliably develop a product from them quite yet. I tend to look at design methodology as 3 basic stages; The initial feasibility stage (can we reasonably target the speed, power and area specifications put forth by management in a schedule that is achievable?) Perhaps we call it "Phase-1" or "First-Pass". Then, there is a second stage of development, maybe call it "Phase-2" or "Second-Pass" where you attempt to get every feature designed and some preliminary layout that can be extracted. Somewhat of a hybrid phase where you gain some insight and perhaps allow for course corrections (i.e., architects decide that they need more bits for Error Correction Code instead of just Parity checking. Or perhaps a speed/power trade-off seems apparent and we must react to changing how sense amps are interleaved to handle the new request. Finally, of course, by "Phase-3" or "Final-Pass" you are racing against the clock to complete all necessary analysis and verification including very detailed parasitic extraction from layout (many CAD tools need to be successfully run & completed) to provide management with an audit of deliverable collateral to a "customer" which is the next level of physical integration and system analysis. This final stage of completion for the custom circuit designer culminates in delivery of GDS-II commonly called "Tape Out". This is a key milestone on anyone's Gantt Chart to produce a chip like a microprocessor or SOC (System-On-Chip).
Using LTspice as a simulation tool (as opposed to OrCAD, Sabre or Pspice), I made an attempt to enter the schematic of the fundamental "building block",... the bitcell. From Figure-1 above, the Harper cell can be entered into the CAD tool as a schematic and then a netlist of the components written out as a file to be simulated. You essentially want to do this since we will build up the SPICE model hierarchically. There are many reasons to do this, but, one of them is to match (at some point in the hierarchy) the equivalent group of devices, call it a "sub cell"or a "sub circuit", in the equivalent physical layout that eventually determines how manufacturing will create the layers required to make the devices in silicon. By matching certain levels of hierchary, you provide a more modular approach to building up the custom macro for completion (top cell). This allows the layout designer (or Mask Designer) an opportunity to quickly run just that sub-cell for layout verification or LVS (Layout vs Schematic).
​
​
​
​
​
​
​
​
​
​
​
​
​
​
​
A similar subckt model can be built for the CTS cell (with similar ports, such as WL, DL, BL and BLB)