Part 4
Bitcell Comparison
This section is "on-going"
If y'all have been following; I've been adding a new page on the 15th of each month (following the Femto idea). The next big step in being able to test out circuit designs is to have the ability to simulate the behavior of the design under various conditions (process variation, power supply sweep and temperature specifications). Before we can really build up a full netlist of a design, we will need some sort of transistor model that will accurately represent the performance of the devices in the SPICE simulator. The classic device model is usually some variation of the Gummel-Poon integral-charge control model.
The Gummel-Poon model defaults to the large signal Ebers-Moll model by leaving out certain parameters. If we only define the parameters; IS, BF, NF, ISE, IKF, and NE,... these determine the forward current gain characteristics, and VAF and VAR determine the output conductance for forward and reverse regions. I need to investigate a little bit further to come up with a reasonable "small signal" bipolar device model in something like 1um or 2um technology before we can get good results. The bitcell will be difficult to model since the schottky is integrated into the NPN or load resistor itself and is a vertical device. The PNP device will be a lateral device with low gain. In any case, I don't want the device model so sophisticated that LTSpice has difficulty converging or takes up too much CPU simulation time!